1. Technical Field
The present invention relates to semiconductor processing, and more particularly to a gate tie-down structure that permits gate contacts in active areas and self-aligns these gate contacts with source/drain contacts.
2. Description of the Related Art
In conventional complementary metal oxide semiconductor (CMOS) processing, gate contacts are formed over shallow trench isolation (STI) regions. Gate contacts connect a gate line to upper metal layers in device designs. In many instances, providing the gate contacts in STI regions can result is a large amount of chip area being lost.
Gate tie-down structures or regions provide a connection between the gate contact and a source/drain (S/D) region contact. The formation of a gate tie-down structure may result in shorts between a silicide region of the S/D region or with conductive material of an adjacent gate. This is due in part to the small margins of dielectric materials between these structures and the close proximity of the conductive bodies.